dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/9 msm9841 ? semiconductor fedl9841-04 general description the msm9841 is a mono/stereo record and playback lsi with a built-in 1k bit fifo for easy interface with external systems or non-semiconductor memory. it utilizes multiple record and playback modes, including the new adpcm2 algorithm, which allows for even higher quality sound reproduction. the record and playback functions of the msm9841 is controlled by an mcu via 8/16-bit bus interface. features ? 16/8-bit bus interface support ? fifo capacity: user-definable (256/512/1024 bits) (buffering time of 32 ms when using 8 khz sampling frequency, 4-bit adpcm2/adpcm, and in monaural playback) ? supports four compression algorithms for record and playback: 4, 5, 6, 7, 8-bit adpcm2; 4-bit adpcm; 8; 16-bit pcm; and 8-bit nonlinear pcm ? sampling frequency: 4.0 khz, 6.4 khz, 8.0 khz, 12.8 khz, 16.0 khz, 32.0 khz* (fosc=4.096 mhz) ? sampling frequency: 22.05 khz*, 44.1 khz* (fosc=5.6448 mhz) ? for the built-in adc, set the sampling frequency at 16 khz or less. ? dma interface support ? volume control (8 steps: 0 db to C21 db) ? built-in 14-bit a/d converter ? built-in 14-bit d/a converter ? built-in low pass filter (lpf) : (input side: analog lpf) : (output side: digital lpf) ? power supply voltage: 2.7 v to 5.5 v ? package: 56-pin plastic qfp (qfp56-p-910-0.65-2k) (product name: MSM9841GS-2K) *note 32 khz, 22.05 khz and 44.1 khz are available only for playback. ? semiconductor msm9841 recording and playback lsi with built-in fifo this document contains minimum specifications. for full specifications, please contact your nearest oki office or representative. this version: jul. 2000 previous version: jun. 1999 fedl9841-04
2/9 msm9841 ? semiconductor fedl9841-04 block diagram mout lout aoutl aoutr min emp mid d15 to d0 wr rd cs d/ c fifo mcu i/f adsd dasd siock test0 test1 dreql dackl iow ior vck xt xt reset input side lpf volume controller adpcm2/adpcm/pcm/non-linear pcm synthesizer dma i/f timing controller external dac/adc i/f lin ful/dreqr ch/dackr busy adc output side lpf dac dac sg av dd agnd dv dd dgnd adpcm2/adpcm/pcm analyzer output side lpf
3/9 msm9841 ? semiconductor fedl9841-04 pin configuration (top view) nc : no connection 56-pin plastic qfp 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 busy d/ c cs rd wr ful/dreqr mid emp ch/dackr reset nc dv dd av dd aoutr d0 d1 d2 d3 nc d4 d5 d6 d7 nc d8 d9 d10 d11 56 nc 55 54 53 52 51 50 49 48 47 46 45 44 43 xt xt ior iow dreql dackl dgnd test1 test0 vck adsd dasd siock 15 nc 16 17 18 19 20 21 22 23 24 25 26 27 28 d12 d13 d14 d15 nc dgnd agnd min mout lin lout sg a outl
4/9 msm9841 ? semiconductor fedl9841-04 pin descriptions symbol type description for 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs to input or output data to and from an external memory. otherwise, these pins are configured to be inputs only. for 16-bit interface, these pins are a bidirectional data bus to input or output data to and from an external microcontroller and memory. birirectional data bus to input or output data and output status to and from an external microcontroller and memory. write pulse input pin. this pin pulses "l" when command or voice data is input to d15-d0 pins. read pulse input pin. this pin pulses "l" when status or voice data is output to d15-d0 pins. accepts write pulse and read pulse when this pin is "l". does not accept write pulse and read pulse when this pin is "h". voice data is input or output to and from d15-d0 pins when this pin is "h". command is input to and status is output from d7-d0 pins when this pin is "l". this pin outputs a "l" level during recording, playback or pause. "h" level indicates that there is no data in fifo memory. active "h" can be changed to active "l" by command input. "h" level indicates that more than half of the fifo memory space is filled with data. during playback, voice synthesis starts when mid changes to "h" level. active "h" can be changed to active "l" by command input. this pin outputs a synchro signal for voice data input/ output when non-use of fifo is selected. "h" level indicates that fifo memory is full of data. during playback, this pin is "h" and data cannot be written in fifo memory. active "h" can be changed to active "l" by command input. when dma transfer and stereo playback are selected, "h" level dreqr outputs a signal to request a dma transfer. active "h" can be changed to active "l" by command input. when stereo playback is selected and ch is "h", the emp, mid or ful pin outputs the status of right fifo memory. when ch is "l", the emp, mid or ful pin outputs the status of left fifo memory. set this pin to "l" during recording and monophonic playback. when dma transfer and stereo playback are selected, dackr is selected. in this case, input a dma transfer acknowledge signal to dackr. when dackr is "l", the iow signal is accepted. active "l" can be changed to active "h" by command input. when dma transfer is selected, "h" level dreql outputs a signal to request a dma transfer. when stereo playback is selected, "h" level dreql outputs a signal to request a dma transfer. active "h" can be changed to active "l" by command input. input to dackl a signal when dma transfer is permitted by the dma controller. when dackl is "l", ior and iow signals are accepted. when stereo playback is selected, input to dackl a dma transfer acknowledge signal for left fifo memory. active "l" can be changed to active "h" by command input. if dma transfer is not used, set this pin to "h" level. d15-d8 i/o d7-d0 i/o wr i rd i cs i d/ c i busy o emp o mid o ful/dreqr o ch/dackr i dreql o dackl i
5/9 msm9841 ? semiconductor fedl9841-04 pin descriptions symbol type description read pulse input pin to read data of msm9841 during dma transfer. if dma transfer is not used, set this pin to "h" level. 16-bit serial data input pin when external adc is used. if external adc is not used, set this pin to "l" level. 16-bit serial data output pin when external dac is used. synchronizing clock for 16-bit serial data input/output when external adc or dac is used. digital power supply pin. insert a minimum 0.1 m f bypass capacitor between this pin and dgnd pin. ior i adsd i dasd o siock o xt xt i o vck o reset i test0 test1 i sg o min lin i mout lout o aoutl o aoutr o dv dd oscillator connection pins. when external clock is used, input clock into xt pin and leave xt pin open. outputs sampling frequency selected at recording or playback. vck pin is used as a synchronizing signal when external adc or dac is used. when this pin is "l" level input, the lsi is initialized. pins for testing. set the pins to "l". analog circuit signal ground output pin. inverting input pin for built-in op amplifier. noninverting input pin is connected to sg (signal ground) internally. mout is the output of internal op amplifier to min, and lout is to lin. left analog output pin from built-in lpf. this is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. right analog output pin from built-in lpf. this is the output pin of playback wavefroms, and is connected to the amplifier for driving speakers. dgnd digital gnd pin. av dd analog power supply pin. insert a minimum 0.1 m f bypass capacitor between this pin and agnd pin. agnd analog gnd pin. iow i write pulse input pin to write external memory data to msm9841 during dma transfer. if dma transfer is not used, set this pin to "h" level.
6/9 msm9841 ? semiconductor fedl9841-04 absolute maximum ratings parameter symbol condition rating unit power supply voltage v dd ta=25c C0.3 to +7.0 v input voltage v in ta=25c C0.3 to v dd +0.3 v storage temperature t stg C55 to +155 c recommended operating conditions parameter symbol condition range unit power supply voltage v dd dgnd=agnd=0v 2.7 to 5.5 v operating temperature t op C40 to +85 c master clock frequency f osc typ. mhz 4.096 4.0 6.0 min. max. electrical characteristics dc characteristics parameter symbol condition min. typ. max. unit v ih v dd 0.85 v v il v dd 0.2 v v oh i oh =C40 m av dd C0.3 v v ol i ol =2 ma 0.45 v i ih1 v ih =v dd 10 m a i ih2 v ih =v dd 20 m a i il1 v il =gnd C10 m a i il2 v il =gnd C20 m a i dd dv dd =av dd =4.5 to 5.5 v, 1530ma at power down, without load ta=C40 to +70c 10 m a i dds at power down, without load ta=C40 to +85c 50 m a high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input current (*1) high-level input current (*2) low-level input current (*1) low-level input current (*2) operating current consumption stanby current consumption dv dd =av dd =2.7 to 5.5v, dgnd=agnd=0v, ta=C40 to +85c high-level input current (*3) i ih3 dv dd =av dd =4.5 to 5.5 v, v ih =v dd 30 150 300 m a dv dd =av dd =2.7 to 3.6 v, v ih =v dd 10 50 100 m a fosc=4.096 mhz, whithout load dv dd =av dd =2.7 to 3.6 v, fosc=4.096 mhz, whithout load 1020ma *1 applicable to input pins excluding xt pin. *2 applicable to xt pin. *3 applicable to test0 pin and test1 pin.
7/9 msm9841 ? semiconductor fedl9841-04 cpu interface examples 1) interface when dma controler is used (16-bit bus) memory dma controller mcu m9841 dreql d15 to d0 dackl iow ior rd wr cs d/ c data bus dreqr dackr 2) mcu & external memory interface (16-bit bus) memory mcu m9841 d15 to d0 dackl iow ior rd wr cs d/ c ch emp data bus mid ful
8/9 msm9841 ? semiconductor fedl9841-04 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment package weight (g) oki electric industry co., ltd. rev. no./last revised epoxy resin 42 alloy solder plating ( 3 5 m m) 0.43 typ. 4/nov. 28, 1996 mirror finish qfp56-p-910-0.65-2k
9/9 msm9841 ? semiconductor fedl9841-04 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 2000 oki electric industry co., ltd. printed in japan
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